Integrated circuits have achieved widespread use due in part to their utility in reducing the space required to achieve a given electrical function, with an attendant increase in performance including a reduction in power requirements.
As integrated circuit device sizes decrease and capabilities increase, space available for growing I/O needs decreases. Thus, I/O pins are considered a valuable device resource to be used in only the most efficient manner possible.
One basic feature of all widely used integrated circuits is the use of a binary voltage system. The voltage differential (typically 3 to 5 volts) between logic high and logic low provides an error buffer to ensure that even noisy voltage signals accurately communicate the desired binary I/O signal.
As shown in FIG. 1, a prior art input circuit is normally a simple pad connected to a signal buffer 10 that forwards the signal as appropriate for the device. This circuit merely forwards a received binary signal from an I/O pin without adding any functionality to that signal or the pin from which it is forwarded.
One limitation of the generally accepted binary signal input format is the need for a plurality of physical I/O connections to provide more than two signal options to a device. For example, three clock speed options are selectable by providing the user access to at least two pins for carrying binary signals. Similarly, in the field of Programmable Logic Devices, and particularly Field Programmable Gate Arrays, at least three binary configuration mode selection pins are needed to provide eight (2.sup.3) configuration mode options.
In another available circuit, two or more input buffers with different thresholds are provided to receive the input signal. Such a circuit may include one buffer having a low threshold (e.g., 1.5 volts) and second buffer having a higher threshold (e.g., 3.0 volts). Three logic states can then be derived from the buffer outputs, corresponding to input signal levels 0 to 1.5 volts, 1.5 to 3.0 volts, and above 3.0 volts. However, such a circuit narrows the margin of error for accurately reading unstable input signals and requires additional control logic for the input signal source to distinguish the three voltage levels.
Thus, a circuit which enhances the functionality of binary input signals and binary I/O structures without narrowing the margin of error or increasing the number of pins would be advantageous.